Flash memory devices are used in any application for storing of binary digits (or bits) of information that may be maintained even when the flash memory devices are not powered. In general, each flash memory device comprises a matrix of memory cells. Each memory cell typically comprises a floating gate MOS transistor. Such a transistor has a bulk terminal, a drain terminal, a source terminal, and a control (gate) terminal, similarly to a standard metal oxide semiconductor (MOS) transistor, and a further control (floating gate) region buried in an oxide layer so as to be electrically insulated.
As known, programming operations (electric charges trapped in the floating gate, this condition determining a high threshold voltage of the transistor), erasing operations (floating gate free from electrical charges, this condition determining a low threshold voltage of the transistor), reading operations (transistor being crossed by a conduction current depending on the threshold voltage), soft-programming operations (restoring of depleted memory cells, i.e. memory cells whose transistors, as having threshold voltages below the low threshold voltage, may be in conduction even when not selected), programming verify operations, erasing verify operations, reading verify operations, and soft-programming verify operations may be performed on each memory cell.
The execution of each of these operations (or memory operations) generally requires that the terminals of the floating gate MOS transistor (and particularly the gate and/or bulk terminals thereof) are suitably biased at respective bias voltages.
For example, during the erasing, programming, programming verify, erasing verify, reading verify, and soft-programming verify operations, the bias voltage applied to the gate terminals of the selected memory cells is equal to −10V, 9V, 6.3V, 4.4V, 5.3V and 2.8V, respectively, whereas during the erasing/soft-programming operation the bias voltage applied to the bulk/gate terminals comprises (voltage) pulses having progressively increasing values (for example, from 4V to 10.75V with a 0.3V step, and from 2.5V to 7V with a 0.125V step, respectively).
Therefore, the execution of each one of these operations generally requires that the bias voltages are generated quickly and with high granularity. For this purpose, each flash memory device typically comprises a digital-to-analog converter (hereinafter, DAC, “Digital (to) Analog Converter” converter) for generating the bias voltage from a corresponding digital value.
In particular, the DAC comprises a conversion block (typically, a R-2R resistor ladder network) for receiving the digital value and providing a corresponding analog value, and an amplification block (for example, an operational amplifier) for amplifying (by an appropriate amplifying factor, or gain) such analog value thereby obtaining the bias voltage. The gain of the amplification block is determined by a resistive (partition) network (for example, arranged, with respect to the operational amplifier, in feedback configuration). To obtain a sufficient gain of the amplification block, such a resistive network typically comprises a resistor having high resistance (for example, of the order of MΩ), and a resistor having a relatively low resistance (for example, of the order of hundreds of kΩ).
However, since the resistive network is subject to non negligible tolerances (for example, actual resistance values different from nominal resistance values), it may be desirable to include compensation capacitors. Furthermore, the resistor having high resistance introduces (by virtue of the relatively high number of diffusions or metallization for implementation thereof) significant parasitic capacitive couplings. However, the compensation capacitors and the parasitic capacitive couplings affect the performance of the DAC (as determining, for example, a limitation of its bandwidth, and hence of its speed).
Furthermore, these resistors (and particularly the resistor having high resistance) determine high area occupation by the DAC (and, hence, by the flash memory device), as well as an excessive electric power consumption.